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  1. /**
  2. *
  3. * \file
  4. *
  5. * \brief This module contains SAMD21 BSP APIs implementation.
  6. *
  7. * Copyright (c) 2018 Atmel Corporation. All rights reserved.
  8. *
  9. * \asf_license_start
  10. *
  11. * \page License
  12. *
  13. * Redistribution and use in source and binary forms, with or without
  14. * modification, are permitted provided that the following conditions are met:
  15. *
  16. * 1. Redistributions of source code must retain the above copyright notice,
  17. * this list of conditions and the following disclaimer.
  18. *
  19. * 2. Redistributions in binary form must reproduce the above copyright notice,
  20. * this list of conditions and the following disclaimer in the documentation
  21. * and/or other materials provided with the distribution.
  22. *
  23. * 3. The name of Atmel may not be used to endorse or promote products derived
  24. * from this software without specific prior written permission.
  25. *
  26. * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
  27. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  29. * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
  30. * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  34. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  35. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  36. * POSSIBILITY OF SUCH DAMAGE.
  37. *
  38. * \asf_license_stop
  39. *
  40. */
  41. #include "bsp/include/nm_bsp.h"
  42. #include "common/include/nm_common.h"
  43. #include "timer.h"
  44. #include "define.h"
  45. #include "BoardCfg.h"
  46. //#include <plib.h>
  47. //#include "atmel_start.h"
  48. //#include "winc_init.h"
  49. #ifndef CONF_WINC_EXT_INT_PIN
  50. #define CONF_WINC_EXT_INT_PIN 0
  51. #endif
  52. static tpfNmBspIsr gpfIsr = NULL;
  53. void __ISR(_EXTERNAL_0_VECTOR , ipl3) chip_isr(void)
  54. //static void chip_isr(void)
  55. {
  56. if (gpfIsr)
  57. {
  58. gpfIsr();
  59. }
  60. IFS0bits.INT0IF = 0;
  61. }
  62. /*
  63. * @fn nm_bsp_init
  64. * @brief Initialize BSP
  65. * @return 0 in case of success and -1 in case of failure
  66. */
  67. sint8 nm_bsp_init(void)
  68. {
  69. gpfIsr = NULL;
  70. //
  71. //JFM Not necessary, we know our timer base is 1ms...
  72. // /* Make sure a 1ms Systick is configured. */
  73. // if (!(SysTick->CTRL & SysTick_CTRL_ENABLE_Msk && SysTick->CTRL & SysTick_CTRL_TICKINT_Msk)) {
  74. // delay_init(SysTick);
  75. // }
  76. return M2M_SUCCESS;
  77. }
  78. /**
  79. * @fn nm_bsp_deinit
  80. * @brief De-iInitialize BSP
  81. * @return 0 in case of success and -1 in case of failure
  82. */
  83. sint8 nm_bsp_deinit(void)
  84. {
  85. return M2M_SUCCESS;
  86. }
  87. /**
  88. * @fn nm_bsp_reset
  89. * @brief Reset NMC1500 SoC by setting CHIP_EN and RESET_N signals low,
  90. * CHIP_EN high then RESET_N high
  91. */
  92. void nm_bsp_reset(void)
  93. {
  94. // GP_DEBUG_1_PIN = 1;
  95. WIFI_CHP_EN_PIN = 0;
  96. WIFI_CHP_RST_PIN = 0;
  97. // Sleep(1); //JFM
  98. Sleep(100);
  99. WIFI_CHP_EN_PIN = 1;
  100. // Sleep(5); JFM
  101. Sleep(150);
  102. WIFI_CHP_RST_PIN = 1;
  103. // GP_DEBUG_1_PIN = 0;
  104. // gpio_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, false);
  105. // gpio_set_pin_level(CONF_WINC_PIN_RESET, false);
  106. // nm_bsp_sleep(1);
  107. // gpio_set_pin_level(CONF_WINC_PIN_CHIP_ENABLE, true);
  108. // nm_bsp_sleep(5);
  109. // gpio_set_pin_level(CONF_WINC_PIN_RESET, true);
  110. }
  111. /*
  112. * @fn nm_bsp_sleep
  113. * @brief Sleep in units of mSec
  114. * @param[IN] u32TimeMsec
  115. * Time in milliseconds
  116. */
  117. void nm_bsp_sleep(uint32 u32TimeMsec)
  118. {
  119. Sleep(u32TimeMsec);
  120. // while (u32TimeMsec--) {
  121. // delay_ms(1);
  122. // }
  123. }
  124. /**
  125. * \internal Get the PIO hardware instance
  126. *
  127. * \param[in] pin The PIO pin
  128. *
  129. * \return The instance of PIO hardware
  130. */
  131. /*
  132. * @fn nm_bsp_register_isr
  133. * @brief Register interrupt service routine
  134. * @param[IN] pfIsr
  135. * Pointer to ISR handler
  136. */
  137. void nm_bsp_register_isr(tpfNmBspIsr pfIsr)
  138. {
  139. gpfIsr = pfIsr;
  140. //
  141. // ext_irq_register(CONF_WINC_EXT_INT_PIN, chip_isr);
  142. }
  143. /*
  144. * @fn nm_bsp_interrupt_ctrl
  145. * @brief Enable/Disable interrupts
  146. * @param[IN] u8Enable
  147. * '0' disable interrupts. '1' enable interrupts
  148. */
  149. void nm_bsp_interrupt_ctrl(uint8 u8Enable)
  150. {
  151. if(u8Enable == 0)
  152. {
  153. IEC0bits.INT0IE = 0;
  154. }
  155. else
  156. {
  157. IEC0bits.INT0IE = 1;
  158. }
  159. // _ext_irq_enable(CONF_WINC_EXT_INT_PIN, u8Enable);
  160. }