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[]
[{"$nulls":7},"Facture 1"]
["Date","7 mai 2012","Heure Début","Heure Fin","Durée",null,null,"Facture 2"]
[null,null,"19:30:00","20:30:00","01:00:00",null,null,"Facture 3"]
["Activités","Setup"]
[]
[]
["Date","10 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"16:15:00","19:00:00","02:45:00"]
["Activités","Code - HallGenerator"]
[]
[]
["Date","15 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"15:30:00","17:30:00","02:00:00"]
["Activités","Adapt SPI driver for FIFO operation"]
[null,"Develop scheduler concept"]
[]
["Date","17 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","19:30:00","02:30:00"]
["Activités","Resolver acquisition module and interrupt priority management"]
[]
[]
["Date","20 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"14:45:00","18:15:00","03:30:00"]
["Activités","Setup CUMux board for development"]
[null,"Resolver acquisition module and interrupt priority development"]
[]
["Date","21 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"07:30:00","12:00:00","04:30:00"]
["Activités","Setup CUMux board for development (Serial ports)"]
[null,"Implement ADC driver"]
[]
["Date","22 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"18:00:00","19:30:00","01:30:00"]
["Activités","Implement Halls Acquistion module"]
[]
[]
["Date","24 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"19:00:00","20:00:00","01:00:00"]
["Activités","Modifiy UART to use CUMux as dev board."]
[]
[]
["Date","26 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"06:45:00","10:45:00","04:00:00"]
["Activités","Create CUMux board harness and hook communication to PA"]
[null,"Setup console UART port on CUMux board."]
[]
["Date","26 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"13:45:00","15:30:00","01:45:00"]
["Activités","Develop PA drive protocol"]
[null,"Connect to PA drive"]
[]
["Date","27 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"08:00:00","09:30:00","01:30:00"]
["Activités","Develop PA drive protocol"]
[]
[]
["Date","27 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","19:00:00","02:00:00"]
["Activités","Test PA Drive communication using CUMux board"]
[null,"Input Capture"]
[null,"DMA"]
["Date","28 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"19:30:00","20:45:00","01:15:00"]
["Activités","Drive Manager development"]
[null,"FPGAInterface development"]
[]
["Date","31 mai 2012","Heure Début","Heure Fin","Durée"]
[null,null,"13:00:00","15:30:00","02:30:00"]
["Activités","Drive Manager development"]
[null,"FPGAInterface development"]
[]
["Date","6 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"15:30:00","17:00:00","01:30:00"]
["Activités","Admin (emails & time log)"]
[]
[]
["Date","7 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"15:45:00","17:15:00","01:30:00"]
["Activités","Mini terminal implementation"]
[null,"Hall acquisition"]
[]
["Date","8 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"15:30:00","18:15:00","02:45:00"]
["Activités"]
[null,"Hall acquisition"]
[]
["Date","9 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"07:45:00","10:30:00","02:45:00"]
["Activités","Drive Manager development"]
[null,"Drive protocol development"]
[]
["Date","21 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"19:00:00","21:00:00","02:00:00"]
["Activités","Meeting avec HCAMP"]
[]
[]
["Date","27 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"17:45:00","19:15:00","01:30:00"]
["Activités","Speed, pos and halls traces"]
[]
[]
["Date","28 juin 2012","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","19:00:00","02:00:00"]
["Activités","Speed, pos and halls traces"]
[]
[]
["Date","12 juillet 2012","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","19:00:00","02:00:00"]
["Activités","Start up new board"]
[null,"Create harness for new PA board"]
[null,"Modify Code for new CPU"]
["Date","13 juillet 2012","Heure Début","Heure Fin","Durée"]
[null,null,"20:00:00",1,"04:00:00"]
["Activités","Setup SPI dongle emulator"]
[null,"Implement CU protocol"]
[]
["Date","14 juillet 2012","Heure Début","Heure Fin","Durée"]
[null,null,"08:30:00","12:30:00","04:00:00"]
["Activités","Program SPI dongle emulator"]
[]
[]
["Date","14 juillet 2012","Heure Début","Heure Fin","Durée"]
[null,null,"19:00:00","21:45:00","02:45:00"]
["Activités","Program SPI dongle emulator"]
[]
[]
["Date","15 juillet 2012","Heure Début","Heure Fin","Durée"]
[null,null,"08:15:00","12:45:00","04:30:00"]
["Activités","Debug SPI Dongle"]
[null,"Debug PA board"]
[null,"Adapt PA Protocol"]
["Date","17 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"18:00:00","21:30:00","03:30:00"]
["Activités","AD2S implementation & Debug"]
[]
[]
["Date","18 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"17:15:00","19:30:00","02:15:00"]
["Activités","Interfaces testing"]
[]
[]
["Date","18 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"20:15:00","22:00:00","01:45:00"]
["Activités","Interfaces testing"]
[]
[]
["Date","19 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"18:15:00","19:15:00","01:00:00"]
["Activités","SPI Dongle debug"]
[]
[]
["Date","24 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"18:00:00","21:00:00","03:00:00"]
["Activités","Drive protocol development"]
[null,"Resolver acquisition timing tuning & state machine development"]
[]
["Date","25 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"19:00:00","22:15:00","03:15:00"]
["Activités","Setup motor"]
[null,"Debug resolver signal"]
[]
["Date","27 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"14:15:00","21:00:00","06:45:00"]
["Activités","Implement Phases acquisition"]
[null,"Debug resolver signal"]
[]
["Date","28 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"07:30:00","14:30:00","07:00:00"]
["Activités","Implement Phases acquisition"]
[null,"Debug resolver signal"]
[]
["Date","29 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"07:00:00","08:30:00","01:30:00"]
["Activités","Drive & AD2S functionnality (config & error management)"]
[]
[]
["Date","30 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"20:00:00","21:30:00","01:30:00"]
["Activités","Create firmware version for FPGA SPI tests @ RhC"]
[null,"Create config files for AMC"]
[]
["Date","31 juillet","Heure Début","Heure Fin","Durée"]
[null,null,"18:30:00","22:00:00","03:30:00"]
["Activités","test modified bard for resolver acquisition"]
[null,"debug halls generation"]
[]
["Date","1 août","Heure Début","Heure Fin","Durée"]
[null,null,"16:45:00","20:30:00","03:45:00"]
["Activités","Add drive protocol funcitonnality"]
[]
[]
["Date","2 août","Heure Début","Heure Fin","Durée"]
[null,null,"12:30:00","19:30:00","07:00:00"]
["Activités","Visit to RhC for integration tests"]
[]
[]
["Date","13 août","Heure Début","Heure Fin","Durée"]
[null,null,"16:15:00","21:00:00","04:45:00"]
["Activités","Debug PA comm"]
[]
[]
["Date","14 août","Heure Début","Heure Fin","Durée"]
[null,null,"16:00:00","19:30:00","03:30:00"]
["Activités","PA loop parameters config and store in NVM"]
[]
[]
["Date","15 août","Heure Début","Heure Fin","Durée"]
[null,null,"17:30:00","19:30:00","02:00:00"]
["Activités","PA loop parameters config and store in NVM"]
[]
[]
["Date","2012-08-16","Heure Début","Heure Fin","Durée"]
[null,null,"19:00:00","22:00:00","03:00:00"]
["Activités","CBIT"]
[null,"Fix drive CRC errors"]
[]
["Date","2012-08-17","Heure Début","Heure Fin","Durée"]
[null,null,"10:30:00","11:45:00","01:15:00"]
["Activités","PA Status & CBIT"]
[]
[]
["Date","2012-08-18","Heure Début","Heure Fin","Durée"]
[null,null,"09:00:00","10:00:00","01:00:00"]
["Activités","CBIT"]
[]
[]
["Date","22 août","Heure Début","Heure Fin","Durée"]
[null,null,"18:30:00","20:00:00","01:30:00"]
["Activités","Debug drive comm"]
[]
[]
["Date","23 août","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","19:15:00","02:15:00"]
["Activités","Debug drive comm"]
[null,"Implement PWM detection"]
[]
["Date","24 août","Heure Début","Heure Fin","Durée"]
[null,null,"07:15:00","10:00:00","02:45:00"]
["Activités","Debug drive comm"]
[]
[]
["Date","27 août","Heure Début","Heure Fin","Durée"]
[null,null,"16:30:00","20:00:00","03:30:00"]
["Activités","Debug drive comm"]
[null,"PWM detection"]
[]
["Date","28 août","Heure Début","Heure Fin","Durée"]
[null,null,"20:00:00","20:45:00","00:45:00"]
["Activités","JIRA"]
[]
[]
["Date","5 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"18:30:00","21:00:00","02:30:00"]
["Activités","Drive comm"]
[null,"Bridge enable polarity"]
[]
["Date","6 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"18:00:00","21:15:00","03:15:00"]
["Activités","add drive enable pin functionnality"]
[null,"change drive config (remove nvm storing and add config comparison at boot)"]
[]
["Date","10 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"16:00:00","21:30:00","05:30:00"]
["Activités","Bootloader"]
[]
[]
["Date","11 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"17:45:00","22:30:00","04:45:00"]
["Activités","Implement NEW SPI Dongle"]
[]
[]
["Date","12 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","22:45:00","05:45:00"]
["Activités","Implement NEW SPI Dongle"]
[null,"PWM detection"]
[]
["Date","13 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"14:30:00","19:00:00","04:30:00"]
["Activités","Visite chez RHc"]
[]
[]
["Date","17 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"17:45:00","23:00:00","05:15:00"]
["Activités"]
[null,"PWM detection with DMA"]
[]
["Date","18 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","21:00:00","04:00:00"]
["Activités","FPGA SPI with DMA and Timer"]
[]
[]
["Date","21 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"19:00:00",1,"05:00:00"]
["Activités","Fix comm driver"]
[]
[]
["Date","22 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"08:00:00","10:45:00","02:45:00"]
["Activités","Add drive comm timeout management in state machine"]
[null,"Fix comm driver"]
[]
["Date","24 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","21:30:00","04:30:00"]
["Activités","Add drive parameters configuration at boot-up"]
[]
[]
["Date","25 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"15:30:00","20:30:00","05:00:00"]
["Activités","Add drive parameters configuration  at boot-up"]
[null,"Fix CU comm"]
[]
["Date","27 septembre","Heure Début","Heure Fin","Durée"]
[null,null,"16:00:00","21:00:00","05:00:00"]
["Activités","Watchdog"]
[]
[]
["Date","6 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"07:15:00","11:30:00","04:15:00"]
["Activités","Bootloader address check"]
[]
[]
["Date","7 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"16:30:00","18:30:00","02:00:00"]
["Activités","Hex file parser"]
[]
[]
["Date","8 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"07:30:00","16:00:00","08:30:00"]
["Activités","Hex file parser"]
[]
[]
["Date","9 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"18:00:00","19:30:00","01:30:00"]
["Activités","Motor Detection"]
[]
[]
["Date","25 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"17:00:00","18:30:00","01:30:00"]
["Activités","DU linker problem"]
[]
[]
["Date","29 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"18:30:00","21:00:00","02:30:00"]
["Activités","DU linker problem"]
[]
[]
["Date","30 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"20:00:00","21:00:00","01:00:00"]
["Activités","DU linker problem"]
[]
[]
["Date","31 octobre","Heure Début","Heure Fin","Durée"]
[null,null,"15:00:00","20:00:00","05:00:00"]
["Activités","Visite chez RHc - DU russe"]
[]
[]
["Date","22 novembre","Heure Début","Heure Fin","Durée"]
[null,null,"18:00:00","21:45:00","03:45:00"]
["Activités","Ajout version du Bootloader dans firmware PA"]
[]
[]
["Date","24 novembre","Heure Début","Heure Fin","Durée"]
[null,null,"06:30:00","08:30:00","02:00:00"]
["Activités","Ajout version du Bootloader dans firmware PA"]

{"sheet":"Activities","index":1,"n_rows":57,"n_cols":64,"rows_kept":57,"merged":[[0,0,0,2],[1,1,1,2],[2,1,2,2],[8,1,8,2],[13,1,13,2],[18,1,18,2],[23,1,23,2],[28,1,28,2],[37,1,37,2],[44,1,44,2]],"flags":["formulas_cached_only"]}
["PA BOARD DEVELOPMENT HOURS BREAKDOWN",{"$nulls":3},"Date","7-05-2012","10-05-2012","15-05-2012","17-05-2012","20-05-2012","21-05-2012","22-05-2012","24-05-2012","26-05-2012","27-05-2012","28-05-2012","31-05-2012","06-06-2012","07-06-2012","08-06-2012","09-06-2012","21-06-2012","27-06-2012","28-06-2012","12-07-2012","13-07-2012","14-07-2012","15-07-2012","17-07-2012","18-07-2012","19-07-2012","24-07-2012","25-07-2012","27-07-2012","28-07-2012","29-07-2012","30-07-2012","31-07-2012","01-08-2012","02-08-2012","13-08-2012","14-08-2012","15-08-2012","16-08-2012","17-08-2012","18-08-2012","22-08-2012","23-08-2012","24-08-2012","27-08-2012","28-08-2012","05-09-2012","06-09-2012","10-09-2012","11-09-2012","12-09-2012","13-09-2012","17-09-2012","18-09-2012","21-09-2013","22-09-2014","24-09-2012","25-09-2013"]
[null,"Activities",null,"Est. Hours","Remaining"]
["NA-772","AD2S RDC"]
["NA-773",null,"Write hardware drivers",4,0,{"$nulls":3},2.5,{"$nulls":19},1.5]
["NA-774",null,"Implement Functionality",8,0,{"$nulls":4},2.5,{"$nulls":18},2,2,null,null,1.5]
["NA-775",null,"Implement interfaces (C.U., Halls,BIT,Trace)",4,0,{"$nulls":26},2,2]
["NA-776",null,"Tests",4,0,{"$nulls":28},4]
[{"$nulls":3},20,0]
["NA-777","Hall Sensors Emulation"]
["NA-778",null,"Write hardware drivers",4,3,null,null,1]
["NA-779",null,"Port existing PIC18 code",12,0,null,2.75,{"$nulls":18},2,4,null,null,1,{"$nulls":9},2.25]
["NA-780",25,"Tests (motor or resolver needed)",8,0,{"$nulls":28},0.5,null,null,1.5,3.5,null,2.5]
[{"$nulls":3},24,3]
["NA-781","CU FPGA Interfacing"]
["NA-782",null,"Write hardware drivers",2,0,null,null,1,{"$nulls":8},1]
["NA-783",null,"Implement Comm. Protocol",2,0.25,{"$nulls":24},1,{"$nulls":18},0.75]
["NA-784",0,"Implement Functionality",2,2]
[{"$nulls":3},6,2.25]
["NA-785","Drive Interface"]
["NA-786",null,"Write hardware drivers",2,0,{"$nulls":8},2]
["NA-787",50,"Implement Drive Protocol",16,0,{"$nulls":8},1,1.5,{"$nulls":5},1,{"$nulls":6},4.5,{"$nulls":3},1,{"$nulls":7},2.25,null,null,2,1,null,null,1.5,0.25]
["NA-788",50,"Implement Drive Functionality",24,0,{"$nulls":9},1,0.5,1.5,1.5,null,null,1.75,2,{"$nulls":12},2,1.5,{"$nulls":4},4.75,3.5,{"$nulls":5},2,2]
[{"$nulls":3},42,0]
["NA-789","C.U. (ARM) Interface"]
["NA-790",50,"Write hardware drivers",2,1.25,{"$nulls":10},0.75]
["NA-791",50,"Define CU Communication protocol",8,2.5,{"$nulls":48},5.5]
["NA-792",25,"Implement CU communication Protocol",16,1,{"$nulls":25},1,{"$nulls":18},3.5,null,2.5,3.25,null,4.75]
[{"$nulls":3},26,4.75]
["NA-802","Traces"]
["NA-803",null,"Write Data acquisition hardware drivers",24,16,{"$nulls":5},2.5,{"$nulls":3},1,{"$nulls":18},2,2.5]
["NA-804",null,"Implement timers drivers and  parametrisation",8,1.75,{"$nulls":6},0.5,{"$nulls":43},5.75]
["NA-805",null,"Implement Trace Console backbone",32,22.25,{"$nulls":51},4.5,5.25]
["NA-806",null,"Implement CU and console drivers",4,4]
["NA-807",null,"Define trace behaviour and parameters",6,1.5,{"$nulls":6},1,{"$nulls":10},1.5,2]
["NA-808",null,"Implement tracing algorithms",48,35,{"$nulls":13},1.5,2.5,{"$nulls":6},2.75,{"$nulls":7},2.5,{"$nulls":3},3.75]
["NA-809",50,"Tests and corrections",24,3.25,{"$nulls":4},1,{"$nulls":49},5,2.75,4.5,5,2.5]
[{"$nulls":3},146,83.75]
["NA-793","Built-In Tests"]
["NA-794",0,"Write Data Acquisition hardware drivers",4,2,{"$nulls":39},1.25,{"$nulls":5},0.75]
["NA-795",0,"Define BITs",4,3,{"$nulls":40},1]
["NA-796",0,"Implement Drive BITS acquisition",8,2,{"$nulls":38},2,{"$nulls":14},4]
["NA-797",0,"Implement PIC32 BITS acquisition",8,8]
["NA-798",0,"Update CU protocol",4,4]
[{"$nulls":3},28,19]
[null,"Other tasks"]
["NA-799",null,"Board startup",4,0,1,{"$nulls":4},2,{"$nulls":14},1]
["NA-800",null,"Firmware clean-up upon board reception",4,0,{"$nulls":7},1,{"$nulls":11},2,1]
[{"$nulls":3},8,0]
[]
[null,"Total Estimated Software Hours",null,300,112.75]
[]
[]
[null,"Hardware Hours",{"$nulls":11},2.75]
[]
[{"$nulls":4},190,1,2.75,2,2.5,3.5,4.5,1.5,1,5.75,3.5,1.25,2.5,1.5,1.5,2.5,2.75,2,1.5,2,2,4,6.75,4.5,3.5,4,1,3,3.5,6.5,7,1.5,1.5,3.5,3.75,7,4.75,3.5,2,3,1.25,1,1.5,2.25,2.75,3.5,0.75,2.5,3.25,5.5,4.75,5.75,4.5,5.25,4,5,2.75,4.5,5,2.5]
[]
[{"$nulls":3},0]

{"sheet":"TODO","index":2,"n_rows":22,"n_cols":6,"rows_kept":22,"flags":["formulas_cached_only"]}
[]
[null,"FIX clock rate"]
["x","Implement SPI buffered mode",null,null,"OK (not available on this PIC)"]
["x","Fixcomm crash ??? With high 150KHz resolver acquisition."]
["x","Setup drive configuration mechanism",{"$nulls":3},"OK"]
[null,"Replace TimerStart() with TimerReset() for all timer kicks…"]
[null,"Implement PWM detection"]
[null,"Finish CU serial comm implementation"]
[null,"Implement Drive Enable pin OK"]
[null,"Use Watchdog"]
[null,"Use bootloader"]
[null,"Avoid Deadlocks by adding a timer to Drive init in DriveManager state machine"]
[null,"Send bridge control pin polarity"]
[]
[]
[]
[]
[]
[]
[null,"Comm debug"]
[null," essayer de réduire la freq du resolver"]
[null,"vérifier l'état des buffers en debug quand ça arrive"]